1. Field of the Invention
The present invention relates to a cache memory control circuit and a processor, and more particularly to a cache memory control circuit of a cache memory having a plurality of ways, and a processor.
2. Description of the Related Art
Cache memories are widely used in processors in order to access data stored in a main memory at high speed. The cache memory is provided between the central processing unit (hereunder, referred to as “CPU”) and the main memory.
Some cache memories have a plurality of ways that have the same entry address. In those kinds of cache memories, an address decoder simultaneously performs a frame address comparison, i.e. a tag comparison, with respect to all the ways based on entry addresses in address data from the CPU, and outputs words that are shown by word addresses to the CPU from among the data that is read from the cache memory.
Recently, in order to reduce the power consumption of processors, cache memories that have two access modes have been proposed (for example, see Japanese Patent Application Laid-Open Publication No. 2002-236616). According to the cache memory proposed in Japanese Patent Application Laid-Open Publication No. 2002-236616, a tag comparison is performed for all ways in a normal access mode, while in a unique access mode a tag comparison is performed only for a selected way. Thus, in the unique access mode, the power consumption is decreased because only the minimum required memory region operates.
However, in the unique access mode described in the above proposal, a cache memory region to be used is limited, and hence even when the same software is operated, there are cases in which the frequency of cache misses increases in comparison to the normal access mode. In such a case, many cache refill operations occur and thus lower power consumption is not adequately performed.
The present invention was made in consideration of the above described problem, and an object of the invention is to provide a cache memory control circuit and a processor that can cause a cache memory to operate in an access mode that operates with the lowest possible power consumption while maintaining a cache hit performance that is equivalent to that of a normal access mode.